Development of an innovative, integrated cryptography module with zero-knowledge security within an efficient preprocessor for RISC-V processors
WIZnet, with partners Red Semiconductor and the University of Sheffield aim to develop an innovative and inherently secure cryptography module that is monolithically integrated into Red Semiconductor's highly-efficient 'Versatile Intrinsic Structured Computing' (VISC) preprocessor. The aim is to eliminate previous design-typical weaknesses of Trusted Platform Modules (TPMs) by integrating WIZnet's 'Symbiotic Security' concept at the hardware level. The resulting preprocessor will aim to be application-specific configurable for different IoT systems and thus will ideally be used as a secure TPM. Even in the event of successful attacks on the cryptographic module, the 'Zero Knowledge Initial Enrolment' (ZKIE) principle is intended to enable the hardware to be reset to a secure base state with subsequent reconfiguration.
Project Objectives
A central aspect of the development of the cryptographic module is its integration into the VISC preprocessor architecture of RED Semiconductor. This is upstream of the RISC-V main processor (which will consist of the main security core) and prepares the data in such a way that an increase in efficiency of up to 100 times in certain algorithms is possible. Primarily, this design-in is highly beneficial in terms of improving the potential end-device implementation, as resource and power restrictions come at a premium, as security functionality always increases hardware costs. Therefore, it is necessary to define and develop suitable interfaces between the cryptography module and VISC that on the one hand enable seamless integration into the VISC infrastructure and on the other hand do not compromise the efficiency goals of the architecture, which form the key objectives of this project.
Key Innovation Areas
All three partners will conduct research into design and hardware constraints with the goal of enabling a tremendous leap in the security capabilities of otherwise very resource-constrained processors. Since this is fundamentally supported as a RISC-based processor, a key innovation will be to provide a secure SoC design with efficiency benchmarks to compete with already established market competitors while simultaneously achieving a unique increase in intrinsic hardware security.
Research Consortium and Expertise
The project consortium brings together highly specialised expertise across security architecture, hardware manufacturing, and medical device development, enabling us to research and develop a comprehensive end-to-end solution for secure healthcare IoT applications.
- WIZnet Germany GmbH - WIZnet is responsible for the development of the highly secure cryptography module within the VISC preprocessor as a central innovative component of the entire project. To this end, the individual units necessary for the module will be primarily researched and developed. The focus here is in particular on the secure generation and injection of entropy for the generation of cryptographic keys at runtime. With this development, WIZnet makes it possible - in contrast to purely hardware-based TEE concepts - to generate unique keys for the specific processor, which do not lead to the hardware having to be replaced even in the event of a successful attack.
- RED Semiconductor - RED is playing a central role in the project and is primarily responsible for the successful monolithic integration of the cryptography module into the VISC architecture. In addition to the development of the necessary protocols and interfaces, this includes in particular the intensive testing of the design prototypes presented by WIZnet and TUOS in FPGAs. The main focus is on compliance with the efficiency criteria of the VISC preprocessor.
- University of Sheffield (TUOS) - The Security of Advanced Systems research group supports the definition and testing of the developed interfaces and protocols. The work of the University is essential to research and develop an inherently secure cryptography module with ZKIE functionality on the one hand and to integrate it monolithically into the VISC architecture on the other hand without causing performance losses.
For technical inquiries, partnership opportunities, or to learn more about the ZeroRISK project, please contact our research team!
